1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a method for fabricating a CUB (capacitor under bit line) capacitor of a semiconductor device.
2. Description of the Related Art
The increasing need for high-speed operation requires high-speed memory devices. Furthermore, a memory device and a logic device typically are merged on the same wafer (so called MML (memory-merged-logic)) in order to construct a system with improved performance. Particularly, a dynamic random access memory (DRAM) and a logic device are merged on a single chip for low cost and high density.
A DRAM device usually comprises a cell array region and a peripheral circuit region. The cell in the cell array region stores binary information and the peripheral circuit drives the cell array, i.e., delivers the information stored in the cell array to the exterior. Accordingly, the cell capacitance of a cell capacitor that stores information plays a key role in the design of a semiconductor memory device. For example, the cell capacitance should be maintained at at least 25 fF to prevent a soft-error rate that can be caused by alpha-particle interference, and to prevent a data-error rate that can be caused by noise. Therefore, high-density techniques that integrate more devices in a given smaller cell area without reducing cell capacitance have become important techniques in the semiconductor memory industry.
However, such high density and high capacitance techniques can give rise to some problems. For example, a step (height difference) can be created between the cell array region where a cell capacitor is formed and the peripheral region, thereby making it difficult to perform a reliable photo-etching process. Accordingly, a CUB (capacitor-under-bit line) structure capacitor rather than a COB (capacitor-over-bit line) structure capacitor is widely used in order to reduce the step between the cell array region and the peripheral circuit region. However, the CUB structure capacitor also has some problems. Namely, in the CUB structure capacitor, an insulating layer formed on the peripheral circuit region is removed after a cell capacitor is formed on the cell array region. Thus, a step between the cell array region and the peripheral circuit region also can be created. Accordingly, it is important to re-form the insulating layer on the peripheral circuit region, and to planarize it for subsequent bit line formation.
In addition, an electrical bridge between storage nodes can arise in DRAM devices due to misalignment and an insufficient process margin caused by the recent ever-decreasing design rule for high memory device. The electrical bridge is a source of a twin bit failure or multi-bit failure, thereby blocking the high density DRAM. Increasing the distance between adjacent storage nodes can minimize the electrical bridge in a box type stack cell structure. The available surface area, however, is reduced too much thereby reducing the capacitance of the cell capacitor.
In an effort to solve the above-mentioned problems, recent disclosures have described making a cylindrical capacitor storage node by using a sacrificial oxide layer. This storage node structure has been called a concave structure. A contact for the lower electrode is formed in the sacrificial oxide layer, a conductive layer fills the contact, and each contact is separated. Finally, the sacrificial oxide layer is removed. The concave structure cell capacitor can further be divided into how the contact is filled with a polysilicon material. The first type of concave structure is one where the contact is completely filled (box type), and the second type of concave structure is one where the contact is partially filled (so-called cylindrical capacitor).
The cylindrical capacitor has some advantages associated with the twin bit failure, when compared to the box type. The cylindrical capacitor is not suitable for miniaturization like the box type, however, because the dielectric layer and the plate electrode are filled into the cylindrical contact. These problems can be severe when hemi-spherical grain (HSG) silicon is formed in the cylinder for high capacitance.
It is a feature of an embodiment of the present invention to provide a method for fabricating a capacitor that can reduce the step between the cell array region and the peripheral circuit region. It is another feature of an embodiment of the present invention to provide a method for fabricating a capacitor that can prevent misalignment of the storage node to the storage node contact, and that can prevent formation of an electrical bridge between adjacent storage nodes. It is an additional feature of an embodiment of the invention to provide a capacitor made by the method that does not have a step between the cell array region and the peripheral circuit region.
To achieve these and other features of the various embodiments of the invention, there is provide a method for fabricating a capacitor of a semiconductor device comprising first providing a semiconductor substrate having a cell array region and a core/peripheral region. At least one first gate line then is formed on the cell region of the semiconductor substrate, and a second gate line is formed on the core/peripheral region of the semiconductor substrate. A first interlayer insulating layer is formed over the first and second gate lines, thereby protecting the first and second gate lines from one another.
The first interlayer insulating layer is patterned in the cell region to expose the semiconductor substrate between the gate lines, and a storage node contact pad and a bit line contact pad are subsequently formed by filling the exposed area with a first conductive material. The method also comprises sequentially forming a second interlayer insulating layer, a second conductive material layer, and an oxide layer on the resulting structure having the storage node and bit line contact pads.
In accordance with the method, the oxide layer and the second conductive material layer are patterned to expose the second interlayer insulating layer over the storage node contact pad thereby forming an opening having sidewalls and a bottom. A dielectric layer and a third conductive layer are sequentially formed on the bottom and sidewalls of the opening. The method then comprises etching the third conductive layer until the dielectric layer on the bottom of the opening is exposed, thereby forming a conductive spacer on the dielectric layer on the sidewalls of the opening, and then subsequently etching the dielectric layer and the second interlayer insulating layer using the conductive spacer as a mask to expose the storage node contact pad. A fourth conductive layer then can be formed to electrically connect the conductive spacer to the storage node contact pad.
In accordance with the method, a third interlayer insulating layer is formed on the resulting structure having the oxide layer and the fourth conductive layer. The third interlayer insulating layer then is patterned together with the oxide layer, the second conductive layer the second interlayer insulating layer, and the first interlayer insulating layer to form a contact hole to the bit line contact pad in the cell array region, and to form a contact hole to the semiconductor substrate outside of the second gate line of the core/peripheral region. An insulating spacer then is formed in the contact hole, and a fifth conductive layer formed in the contact hole to form a contact plug. Finally, the method comprises forming a bit line on the third interlayer insulating layer thereby electrically connecting the bit line to the contact plug.
The present invention also relates to a capacitor of a semiconductor device that is prepared in accordance with the above-described method. The capacitor preferably includes a semiconductor substrate having a cell array region and a core/peripheral region, and at least two gate lines disposed on the semiconductor substrate in the cell array region. The capacitor is further comprised of a storage node contact pad disposed between the at least two gate lines, an opening filled with a fourth conductive material disposed above the storage node contact pad, a conductive spacer comprised of a third conductive material disposed adjacent the opening, a dielectric layer disposed adjacent to the conductive spacer, and a second conductive material layer disposed adjacent to the dielectric layer.
According to the above-mentioned method and capacitor, the opening for a storage node is formed as a contact hole type in a plate electrode. Namely, patterning the plate electrode simultaneously forms the opening for a storage node therein. Furthermore, the storage node comprised of the conductive spacer is formed in the contact hole, and using the spacer as a mask, the underlying layer is etched to an active region or pad. Accordingly, the number of photo-etching process can be reduced by more than half. In addition, since the storage node is formed in a self-aligned manner, misalignment of the storage node and electrical bridging between adjacent storage nodes can be prevented.